In FIG. 1, the 2 shared pixel schematic of a prior art image sensor includes two photodetectors (PD1 and PD2) each having an associated transfer gate (TG1 and TG2) that transfer charge to a common floating diffusion sense node. A row select transistor (RSEL) selects the row for readout, and a reset transistor with a reset gate (RG) resets the common floating diffusion sense node (n+) to a predetermined voltage. A source follower input transistor (SF) senses the voltage on the common floating diffusion sense node (n+) and amplifies the signal. The prior art image sensor in FIG. 2 is a similar concept except that four photodiodes (PD1-PD4) and TGs (TG1-TG4) share common components.
These shared amplifier pixels were intended to produce small pixels with high fill factor with less scaled CMOS processes. With a small pixel, the photodiode can have low charge capacity. Shared amplifier pixels inherently have higher floating diffusion capacitance than un-shared amplifier pixels, due to having multiple floating diffusions connected together. The larger capacitance is a consequence of multiple floating diffusion regions comprising a single charge to voltage conversion node, and due to the parasitic capacitance of the interconnect layers connecting the multiple floating diffusion regions. As a result, it is desired to reduce the floating diffusion capacitance so that an adequate voltage signal swing can be achieved at the sense node.
Consequently, the present invention describes ways to reduce the floating diffusion capacitance in shared amplifier CMOS Active Pixel Sensor (APS) designs.